In the case of the vertical cache, since it would not be part of the first cache levels, then its existence cannot prevent the lower levels of the cache itself from being traversed. We call this a “miss” in the sense that the CPU has not had any aim to find the necessary data and / or instruction, during that time the CPU has a stop or “stall”, since the CPU or GPU it has no data to process. But if you can’t find the data at that cache level then that’s a miss and you need to look at the lower levels. When the CPU searches for a data or an instruction in the system cache hierarchy, it starts with those closest to the CPU itself, if it finds the data then this is what we call a “hit”, referring to what the CPU has targeted in the cache and hit the target. How is the performance of a cache measured?
Since the vertical cache is the last level, it will include all the data that the previous caches require and with its enormous size it will reduce the amount of processor access to RAM, but its efficiency will never be 100%, even with a Very large cache, the program may make a request to a memory address that has not been copied to the last level cache, forcing the processor to access the RAM assigned to it. We have to understand that in a system we never achieve 100% performance and there are always losses, in the case of a processor an important part of the performance loss is in communication with the memory hierarchy, which includes caches. The vertical cache therefore is not intended to increase the processing capacity of a CPU, but its performance. Why a large top-level cache is important here. The sole objective of the cache of every processor is to reduce the access time of the CPU to the RAM memory, but in recent times the transmission of data in the necessary quantities has become a huge energy cost is when architects have to look for the way to reduce the number of accesses in which the CPU or the GPU will make an access to its corresponding memory. So it is best to place a single floor on top of the processor, the memory does not have enough capacity to function as RAM today, but as a last-level cache. Suddenly what sounded like a great idea is no longer so, we have in our hands a very expensive processor to manufacture, in few units and with a worse performance than with the elements separately. Then we can not forget the phenomenon of heat, each new floor forces to lower the clock speed of both the memory and the processor.
It sounds like a great idea and it is possible to do it, but it ceases to be when we consider that with each new memory floor then the number of complete sets between the processor and the memory above them decreases. But how about putting more and more floors of memory on top of the processor? After all, this can be done today.
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How about putting full RAM on top of the processor in a 3D interface? It would not fit us at all due to the high capacity in tens of gigabytes that current RAM requires.
Under this premise, the ideal would be for the RAM to be as close to the processor as possible. Vertical cache instead of vertical memory In the Zen 3 CCD Chiplets there is no memory controller as it is located in the IOD, which is located in another chip, but in a hypothetical APU, the vertical cache would be located above the memory controller, although just earlier in the hierarchy than RAM, but after the higher cache level of the CPU or GPU. What does this have to do with vertical cache? Well, the vertical cache by its position on the chip in an SoC can never be placed before the memory controller in the hierarchy. What they do have in common is the northbridge, which Intel calls “Uncore” and AMD calls “Data Fabric.” No matter what the name is, we are really talking about the same concept. The reality is that today in general terms, all processors are SoCs, in the sense that they make use of several processing elements that can be homogeneous in the sense of using all the same cores or heterogeneous at the same time.
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